Memory cells have traditionally been used to store bits of data. It is also possible to architect a memory cell so that the memory cell is able to perform some simple logical functions when multiple memory cells are connected to the same read bit line. For example, when memory cells A, B, and C are connected to a particular read bit line and are read simultaneously, and the memory cells and read bit line circuitry are designed to produce a logical AND result, then the result that appears on the read bit line is AND(a,b,c) (i.e. “a AND b AND c”), where a, b, and c represent the binary data values stored in memory cells A, B, and C respectively.
By themselves, these computational memory cells and read bit line circuitry allow for a single logical function (e.g. AND) to be performed across multiple memory cells connected to the same read bit line, when read simultaneously. However, in many cases more complex logical functions across multiple memory cells connected to the same read bit line are desirable. Thus, it is desirable to provide additional circuitry associated with each read bit line that facilitates the more complex logical functions and it is to this end that the disclosure is directed.